Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

On the inherent self-interference suppression of full-duplex phased arrays

This paper quantitatively investigates the inherent self-interference (SI) suppression property of dual-polarized fullduplex (FD) linear phased array antennas. The amount of systemic SI suppression is derived for an N×1 array as a function of the phase taper applied on it. The systemic SI suppression occurs due to the destructive interference of signals in different phased array channels. Results indicate more than 10-15 dB SI suppression for most beam directions, and around 2 dB SI suppression for the normal beam direction

SiGe BiCMOS 4-bit phase shifter and T/R module for X-band phased arrays

Current phased array RADAR (RAdio Detection And Ranging) systems conventionally employ transmit/receive (T/R) modules implemented in III-V technologies (such as GaAs and InP) and their usage is mainly restricted to military applications. The next generation phased array systems require thousands of T/R modules with lower cost, size and power consumption. Advances in SiGe BiCMOS process technologies make it a viable option for next generation phased array systems, especially for commercial applications. In the light of these trends, this thesis presents the design of a 4-bit SiGe X-band (8-12 GHz) passive phase shifter and the complete SiGe X-band T/R module, realized in IHP 0.25- m SiGe BiCMOS process. The phase shifter is based on switched lter topology, utilizing a low-pass network for phase shift state and isolated NMOS transistors are used for bypass state. It is composed of 22 , 45 and 90 bits and the 180 bit is realized by cascading two 90 bits. The return loss of each bit is better than 10 dB, the overall phase shifter has an average of 14 dB insertion loss. Minimum RMS phase error of 3 is obtained at 10.1 GHz. RMS phase error is better than 11 at 9.2-10.8 GHz band. The overall phase shifter occupies 0.9 mm2 area, has no DC power consumption and achieves input-referred 1-dB compression point of 15 dBm. The integration of a compact T/R module using the 4-bit phase shifter and the previously developed building blocks such as low-noise ampli er (LNA), power ampli er (PA) and single-pole double-throw (SPDT) switches is presented. The developed SiGe X-band T/R module occupies only 4.9 mm2 chip area. In 9-10 GHz band T/R module achieves a measured gain of 10-11.5 dB in receiver mode and 10.7- 12 dB gain in transmitter mode. A minimum RMS phase error of 5 is achieved at 9 GHz. Noise gure in receiver mode is measured between 4-6 dB while the IIP3 is receive mode is measured as -10.5 dB. Output power at 1-dB compression in transmit mode is 16 dBm. These parameters are achieved with a power consumption of 285 mW

An x-band 6-bit active phase shifter

This paper presents a 6-bit active phase shifter using a new vector-sum method for X-band (8-12 GHz) phased arrays in 0.13 mu m SiGe BiCMOS process. An RC filter is used to generate two orthogonal vectors which are then fed into four VGAs, two using the common-base and two using the common-emitter topology. This generates 4 vectors of 0 degrees, 90 degrees, 180 degrees and 270 degrees which are scaled and added by varying the gains of the VGAs to generate any phase between 0-360 degrees. The gains of the VGAs are adjusted with analog voltage control using the current-steering method. The outputs of the VGAs are connected together with a common load in order to add the vectors in current-domain. The phase shifter achieves < 5.6 degrees RMS phase error over 8-12 GHz and < 3.1 degrees RMS phase error over 9-11 GHz. The phase shifter has a power consumption of 16.6 mW from a 2V supply. The chip size is 850 mu m x 532 mu m including the probing pads. These performance parameters are comparable with the state of the art of the technology in literature

A SiGe BiCMOS bypass low-noise amplifier for x-band phased array RADARs

This paper presents a bypass low noise amplifier (LNA) for X-band phased array applications in 0.25μm SiGe BiCMOS technology. The trade-off between gain and bypass modes is considered to achieve high gain as well as low noise figure for gain mode while maintaining reasonable insertion loss with high power handling capability in bypass mode. In gain mode, the LNA achieves a measured gain of 17-14.2 dB and a noise figure of 1.75-1.95 dB over the 8-12 GHz band while consuming 27.4mW of DC-power. The measured input-referred I-dB compression point (IP 1dB ) is -3.9 dBm at 10 GHz. When operating in bypass mode, the measured insertion loss is 6.5-5.95 dB over the entire X-band with the measured IP 1dB of 15.1 dBm at 10 GHz, and it dissipates only 1μW power. Thanks to the bypassing technique, an increase of about 19 dB is achieved for IP 1dB in bypass mode compare to the gain mode. The measured return losses are better than 10 dB for both operating modes over whole X-band. The effective chip area excluding the pads is 0.3 mm 2

A wideband low noise SiGe medium power amplifier for x-band phased array applications

This paper presents a Medium Power Amplifier (MPA) for X-Band Phased Array RADAR applications in 0.25 mu m SiGe technology. The MPA is designed such that it achieves high output power and low noise simultaneously that enables its use in Transmitter/ Receiver (T/R) core module as a Low Noise Amplifier (LNA). The MPA achieves 23.6dB peak gain and 17.3dB maximum output power at 10GHz with a power consumption of 190mW. Its input and output is matched in a 7 GHz of bandwidth, while its mean Noise Figure (NF) is about 3dB throughout the defined bandwidth. According to authors' knowledge, this work presents state-of-the-art wideband MPA performances in literature, with 7GHz of operational bandwidth and 17.3dBm output power

A wideband high isolation CMOS T/R switch for x-band phased array radar systems

This paper presents an SPDT switch which is designed to operate at 8-12 GHz frequency range (X-Band), as a sub module of the front end circuit of a phased array radar. The switch distinguishes itself from its counterparts with its larger frequency range and higher isolation that is uniformly distributed over its bandwidth. It is fabricated using 0.25 mu m SiGe BiCMOS technology of IHP Microelectronics (Germany). As a new technique, shunt inductors are placed next to shunt transistors in order to improve trade-off between insertion loss and isolation. It has isolation higher than 30 dB in entire band, input referred 1dB compression point is 27.6 dBm, insertion loss is between 2.7-4.1 dB, input and output referred return losses are better than 11 dB in the frequency range of 8-12 Gliz

A k-band 5G phased array RX channel with 3.3-dB NF and 28.5-dB gain in 130-nm SiGe

This paper presents a low-noise K-band phased array receive channel implemented in a 130-nm SiGe BiCMOS process. The IC consists of a cascode LNA, a vector modulator phase shifter (PS), and a current-steering VGA. The LNA employs a shunt inductor at the intermediate node of the cascode for noise reduction purposes. The PS generates I/Q signals by lumped quadrature hybrids for low noise operation. Various process compensation capabilities are employed within the PS to reliably achieve high resolution. The measured results demonstrated a peak gain of 28.5 dB at 24 GHz with a 3-dB bandwidth of 22-27 GHz. The measured noise figure is 3.3 dB, which is better than state-of-the-art among Si-based phased-array channels. For 6-b phase control, the rms phase error is 4∘ and 0.2∘ without and with calibration, respectively; the rms gain error being 1 dB for both cases. For 4-b gain control with 0.4-dB/step, the rms amplitude/phase errors are 0.1-dB/0.5∘. Across different phase settings, the IC has an OP1dB of -2 to -3 dBm, with a power consumption of 48 mW. The total chip area is 1.33 mm2, excluding the pads